128k x 8 static ram cy7c109bn cy7c1009bn cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06430 rev. ** revised february 1, 2006 features ?high speed ?t aa = 12 ns ? low active power ? 495 mw (max. 12 ns) ? low cmos standby power ? 55 mw (max.) 4 mw ? 2.0v data retention ? automatic power-down when deselected ? ttl-compatible inputs and outputs ? easy memory expansion with ce 1 , ce 2 , and oe options functional description [1] the cy7c109bn/cy7c1009bn is a high-performance cmos static ram organized as 131,072 words by 8 bits. easy memory expansion is provided by an active low chip enable (ce 1 ), an active high chip enable (ce 2 ), an active low output enable (oe ), and three-state drivers. writing to the device is accomplished by taking chip enable one (ce 1 ) and write enable (we ) inputs low and chip enable two (ce 2 ) input high. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 16 ). reading from the device is accomplished by taking chip enable one (ce 1 ) and output enable (oe ) low while forcing write enable (we ) and chip enable two (ce 2 ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce 1 high or ce 2 low), the outputs are disabled (oe high), or during a write operation (ce 1 low, ce 2 high, and we low). the cy7c109bn is available in standard 400-mil-wide soj and 32-pin tsop type i packages. the cy7c1009bn is available in a 300-mil-wide soj package. the cy7c1009bn and cy7c109bn are functionally equivalent in all other respects. note: 1. for guidelines on sram system design, plea se refer to the ?system design guidelines ? cypress application not e, available on t he internet at www.cypress.com. 14 15 logic block diagram pin configurations a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer power down we oe i/o 0 ce 2 i/o 1 i/o 2 i/o 3 512x256x8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 11 a 13 a 12 a a 10 ce 1 a a 16 a 9 1 2 3 4 5 6 7 8 9 10 11 14 19 20 24 23 22 21 25 28 27 26 top view soj 12 13 29 32 31 30 16 15 17 18 gnd a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 we v cc a 15 a 13 a 8 a 9 i/o 7 i/o 6 i/o 5 i/o 4 a 2 nc i/o 0 i/o 1 i/o 2 ce 1 oe a 10 i/o 3 a 1 a 0 a 11 ce 2 a 6 a 7 a 16 a 14 a 12 we v cc a 4 a 13 a 8 a 9 oe tsop i top view (not to scale) 1 6 2 3 4 5 7 32 27 31 30 29 28 26 21 25 24 23 22 19 20 i/o 2 i/o 1 gnd i/o 7 i/o 4 i/o 5 i/o 6 i/o 0 ce a 11 a 5 17 18 8 9 10 11 12 13 14 15 16 ce 2 a 15 nc a 10 i/o 3 a 1 a 0 a 3 a 2 [+] feedback [+] feedback
cy7c109bn cy7c1009bn document #: 001-06430 rev. ** page 2 of 9 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc to relative gnd [2] .... ?0.5v to +7.0v dc voltage applied to outputs in high z state [2] ....................................?0.5v to v cc + 0.5v dc input voltage [2] .................................?0.5v to v cc + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... .............. .............. ....... >2001v (per mil-std-883, method 3015) latch-up current ..................................................... >200 ma selection guide 7c109b-12 7c1009b-12 7c109b-15 7c1009b-15 7c109b-20 7c1009b-20 unit maximum access time 12 15 20 ns maximum operating current 90 80 75 ma maximum cmos standby current 10 10 10 ma l 2 2 2 ma operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% industrial ? 40 c to +85 c 5v 10% electrical characteristics over the operating range parameter description test conditions 7c109bn-12 7c1009bn-12 7c109bn-15 7c1009bn-15 7c109bn-20 7c1009bn-20 unit min. max. min. max. min. max. v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il input low voltage [2] ?0.3 0.8 ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ?1 +1 ?1 +1 a i oz output leakage current gnd < v i < v cc , output disabled ?5 +5 ?5 +5 ?5 +5 a i os output short circuit current [3] v cc = max., v out = gnd ?300 ?300 ?300 ma i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 90 80 75 ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce 1 > v ih or ce 2 < v il , v in > v ih or v in < v il , f = f max 45 40 30 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce 1 > v cc ? 0.3v, or ce 2 < 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 10 10 10 ma l2 2 2ma capacitance [4] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 9pf c out output capacitance 8 pf notes: 2. minimum voltage is ?2.0v for pulse durations of less than 20 ns. 3. not more than one output should be shorted at one time. duration of the short circuit should not exceed 30 seconds. 4. tested initially and after any design or process changes that may affect these parameters. [+] feedback [+] feedback
cy7c109bn cy7c1009bn document #: 001-06430 rev. ** page 3 of 9 ac test loads and waveforms 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 30 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) 3 ns 3 ns output r1 480 ? r1 480 ? r2 255 ? r2 255 ? 167 ? equivalent to: venin equivalent 1.73v th switching characteristics [5] over the operating range parameter description 7c109bn-12 7c1009bn-12 7c109bn-15 7c1009bn-15 7c109bn-20 7c1009bn-20 unit min. max. min. max. min. max. read cycle t rc read cycle time 12 15 20 ns t aa address to data valid 12 15 20 ns t oha data hold from address change 3 3 3 ns t ace ce 1 low to data valid, ce 2 high to data valid 12 15 20 ns t doe oe low to data valid 6 7 8 ns t lzoe oe low to low z 0 0 0 ns t hzoe oe high to high z [6, 7] 678ns t lzce ce 1 low to low z, ce 2 high to low z [7] 333ns t hzce ce 1 high to high z, ce 2 low to high z [6, 7] 678ns t pu ce 1 low to power-up, ce 2 high to power-up 0 0 0 ns t pd ce 1 high to power-down, ce 2 low to power-down 12 15 20 ns write cycle [8] t wc write cycle time [9] 12 15 20 ns t sce ce 1 low to write end, ce 2 high to write end 10 12 15 ns t aw address set-up to write end 10 12 15 ns t ha address hold from write end 0 0 0 ns t sa address set-up to write start 0 0 0 ns t pwe we pulse width 10 12 12 ns t sd data set-up to write end 7 8 10 ns t hd data hold from write end 0 0 0 ns t lzwe we high to low z [7] 333ns t hzwe we low to high z [6, 7] 678ns notes: 5. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 6. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 7. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 8. the internal write time of the memory is defined by the overlap of ce 1 low, ce 2 high, and we low. ce 1 and we must be low and ce 2 high to initiate a write, and the transition of any of these signals can terminate the write. the input data set-up and hold timing should be refe renced to the leading edge of the signal that terminates the write. 9. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback [+] feedback
cy7c109bn cy7c1009bn document #: 001-06430 rev. ** page 4 of 9 data retention characteristics over the operating range (low power version only) parameter description conditions min. max unit v dr v cc for data retention no input may exceed v cc + 0.5v v cc = v dr = 2.0v, ce 1 > v cc ? 0.3v or ce 2 < 0.3v, v in > v cc ? 0.3v or v in < 0.3v 2.0 v i ccdr data retention current 150 a t cdr chip deselect to data retention time 0 ns t r operation recovery time 200 s data retention waveform switching waveforms read cycle no. 1 [10, 11] read cycle no. 2 (oe controlled) [11, 12] notes: 10. device is continuously selected. oe , ce 1 = v il , ce 2 = v ih . 11. we is high for read cycle. 12. address valid prior to or coincident with ce 1 transition low and ce 2 transition high. 4.5v 4.5v ce v cc t cdr v dr > 2v data retention mode t r previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce 1 i cc i sb impedance address ce 2 data out v cc supply current [+] feedback [+] feedback
cy7c109bn cy7c1009bn document #: 001-06430 rev. ** page 5 of 9 write cycle no. 1 (ce 1 or ce 2 controlled) [13, 14] write cycle no. 2 (we controlled, oe high during write) [13, 14] notes: 13. data i/o is high impedance if oe = v ih . 14. if ce 1 goes high or ce 2 goes low simultaneously with we going high, the output remains in a high-impedance state. 15. during this period the i/os are in the output state and input signals should not be applied. switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce 1 address ce 2 we data i/o t hd t sd t pwe t sa t ha t aw t sce t sce t wc t hzoe data in valid ce 1 address ce 2 we data i/o oe note 15 [+] feedback [+] feedback
cy7c109bn cy7c1009bn document #: 001-06430 rev. ** page 6 of 9 write cycle no. 3 (we controlled, oe low) [14] switching waveforms (continued) data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t sce t wc t hzwe ce 1 address ce 2 we data i/o note 15 truth table ce 1 ce 2 oe we i/o 0 ?i/o 7 mode power h x x x high z power-down standby (i sb ) x l x x high z power-down standby (i sb ) l h l h data out read active (i cc ) l h x l data in write active (i cc ) l h h h high z selected, outputs disabled active (i cc ) [+] feedback [+] feedback
cy7c109bn cy7c1009bn document #: 001-06430 rev. ** page 7 of 9 ordering information speed (ns) ordering code package diagram package type operating range 12 cy7c109bn-12vc 51-85032 32-lead (400-mil) molded soj commercial cy7c1009bn-12vc 51-85031 32-lead (300-mil) molded soj CY7C109BN-12ZC 51-85056 32-lead tsop type i cy7c109bn-12zxc 51-85056 32-lead tsop type i (pb-free) 15 cy7c109bnl-15vc 51-85032 32-lead (400-mil) molded soj commercial cy7c109bn-15vc 51-85032 32-lead (400-mil) molded soj cy7c1009bn-15vc 51-85031 32-lead (300-mil) molded soj cy7c109bn-15zc 51-85056 32-lead tsop type i cy7c109bn-15zxc 51-85056 32-lead tsop type i (pb-free) cy7c109bn-15vi 51-85032 32-lead (400-mil) molded soj industrial cy7c1009bn-15vi 51-85031 32-lead (300-mil) molded soj 20 cy7c109bn-20vc 51-85032 32-lead (400-mil) molded soj commercial cy7c1009bn-20vc 51-85031 32-lead (300-mil) molded soj cy7c109bn-20vi 51-85032 32-lead (400-mil) molded soj industrial cy7c109bn-20zc 51-85056 32-lead tsop type i commercial cy7c109bn-20zxc 51-85056 32-lead tsop type i (pb-free) please contact local sales representative regarding availability of these parts package diagrams pin 1 i.d .435 .395 .445 .405 .128 .148 .360 .380 .026 .015 .032 .020 dimensions in inches min. max. .025 min. .007 .013 .050 t yp. .720 .730 1 14 15 28 0.004 seating plane 51-85032-*b 28-lead (400-mil) molded soj (51-85032) [+] feedback [+] feedback
cy7c109bn cy7c1009bn document #: 001-06430 rev. ** page 8 of 9 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all product and company names mentio ned in this document may be the tr ademarks of their respective holders. package diagrams (continued) min. max. pin 1 id 0.291 0.300 0.050 typ. 0.007 0.013 0.330 0.350 0.120 0.140 0.025 min. 0.262 0.272 0.697 0.713 0.013 0.019 0.014 0.020 0.032 0.026 a a detail external lead design option 1 option 2 1 14 15 28 0.004 seating plane note : 1. jedec std ref mo088 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.006 in (0.152 mm) per side 3. dimensions in inches 51-85031-*c 28-lead (300-mil) molded soj (51-85031) 51-85056-*d 32-lead tsop i (8x20 mm) (51-85056) [+] feedback [+] feedback
cy7c109bn cy7c1009bn document #: 001-06430 rev. ** page 9 of 9 document history page document title: cy7c109bn / cy7c1009bn 128k x 8 static ram document number: 001-06430 rev. ecn no. issue date orig. of change description of change ** 423847 see ecn nxr new data sheet [+] feedback [+] feedback
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